HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 635

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
15, 14
13, 12
11, 10
Bit Name
ED3
ED2
ED1
Initial
Value
All 0
All 0
All 0
R/W
R/W
R/W
R/W
Description
Channel 3 Pin Active Control
[Input capture mode]
00: Edge detection of CMT_CTR3 pin disabled
01: Edge detection on rising edge of CMT_CTR3 pin
10: Edge detection on falling edge of CMT_CTR3 pin
11: Edge detection on either edge of CMT_CTR3 pin
[Output compare mode]
00: Reserved*
01: 1 is output to CMT_CTR3 pin during active period
10: 0 is output to CMT_CTR3 pin during active period
11: Reserved
Channel 2 Pin Active Control
[Input capture mode]
00: Edge detection of CMT_CTR2 pin disabled
01: Edge detection on rising edge of CMT_CTR2 pin
10: Edge detection on falling edge of CMT_CTR2 pin
11: Edge detection on either edge of CMT_CTR2 pin
[Output compare mode]
00: Reserved*
01: 1 is output to CMT_CTR2 pin during active period
10: 0 is output to CMT_CTR2 pin during active period
11: Reserved
Channel 1 Pin Active Control
[Input capture mode]
00: Edge detection of CMT_CTR1 pin disabled
01: Edge detection on rising edge of CMT_CTR1 pin
10: Edge detection on falling edge of CMT_CTR1 pin
11: Edge detection on either edge of CMT_CTR1 pin
[Output compare mode]
00: Reserved*
01: 1 is output to CMT_CTR1 pin during active period
10: 0 is output to CMT_CTR1 pin during active period
11: Reserved
input
input
input
input
input
input
input
input
input
Rev. 2.00 Feb. 12, 2010 Page 551 of 1330
REJ09B0554-0200