HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 55

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 27 Multifunctional Interface (MFI) .....................................................997
27.1 Features ............................................................................................................................ 997
27.2 Input/Output Pins ............................................................................................................. 999
27.3 Register Descriptions ....................................................................................................... 1000
27.4 Operation.......................................................................................................................... 1012
27.5 Interface (Basic)............................................................................................................... 1014
27.6 Interface (Details) ............................................................................................................ 1016
Section 28 User Debug Interface (H-UDI) ..................................................... 1019
28.1 Input/Output Pins ............................................................................................................. 1021
28.2 Boundary Scan TAP Controllers (EXTEST, SAMPLE/PRELOAD, and BYPASS)....... 1023
28.3 Register Descriptions ....................................................................................................... 1032
28.4 Operation.......................................................................................................................... 1036
28.5 Usage Notes ..................................................................................................................... 1038
26.8.1 Notice about The MMCIF transfer data block size in multiblock read
27.3.1 MFI Index Register (MFIIDX) ........................................................................... 1002
27.3.2 MFI General Status Register (MFIGSR) ............................................................ 1003
27.3.3 MFI Status/Control Register (MFISCR) ............................................................. 1004
27.3.4 MFI Memory Control Register (MFIMCR)........................................................ 1006
27.3.5 MFI Internal Interrupt Control Register (MFIIICR) ........................................... 1008
27.3.6 MFI External Interrupt Control Register (MFIEICR) ......................................... 1009
27.3.7 MFI Address Register (MFIADR) ...................................................................... 1010
27.3.8 MFI Data Register (MFIDATA)......................................................................... 1011
27.4.1 Overview............................................................................................................. 1012
27.4.2 Connections ........................................................................................................ 1013
27.4.3 Memory Map ...................................................................................................... 1013
27.5.1 68-Series 8-Bit Parallel Interface ........................................................................ 1014
27.5.2 80-Series 8-Bit Parallel Interface ........................................................................ 1015
27.6.1 Writing to MFIIDX/Reading from MFIGSR ...................................................... 1016
27.6.2 Reading from/Writing to MFI Register............................................................... 1016
27.6.3 Continuous Data Writing to MFRAM via MFI .................................................. 1017
27.6.4 Continuous Reading from MFRAM via MFI ..................................................... 1017
28.2.1 Boundary Scan Register (SDBSR)...................................................................... 1024
28.3.1 Instruction Register (SDIR) ................................................................................ 1034
28.3.2 Data Register H and L (SDDRH, SDDRL)......................................................... 1034
28.3.3 Interrupt Source Register (SDINT)..................................................................... 1035
28.4.1 TAP Control........................................................................................................ 1036
28.4.2 H-UDI Reset ....................................................................................................... 1037
28.4.3 H-UDI Interrupt .................................................................................................. 1037
command............................................................................................................. 994
Rev. 2.00 Feb. 12, 2010 Page liii of lxxxii
REJ09B0554-0200