HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 732

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
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Quantity
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Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
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When detecting a parity error, the receiver in T = 1 mode does not return an error signal. The
transmitter does not sample error signals or repeat the disputed data.
The operation sequence is as follows.
1. When the SIM is not in use, the data line is in the high-impedance state, fixed at high level by
2. The transmitter starts transmission of one frame of data. The data frame begins with the start
3. The SIM then returns the data line to high impedance. The data line is held at high level by the
4. The receiver performs a parity check.
5. If the transmitter does not receive an error signal, it transmits the next frame.
Rev. 2.00 Feb. 12, 2010 Page 648 of 1330
REJ09B0554-0200
the pull-up resistance.
bit (Ds: low level). This is followed by eight data bits (D0 to D7) and the parity bit (Dp).
pull-up resistance.
If detecting no parity error and receiving the data normally, the receiver waits for the next
frame, without taking further action.
If a parity error has occurred, the receiver outputs an error signal (DE: low level) for
requesting data repetition in T = 0 mode. After outputting an error signal for the specified
duration, the receiver again sets the signal line to high impedance. The signal line returns to
high level by the pull-up resistance. In T = 1 mode, however, the receiver outputs no error
signal when a parity error occurs.
If the transmitter in T = 0 mode receives an error signal, it repeats the disputed data as in step 2
above. In T = 1 mode, however, the transmitter receives no error signals and performs no
repetition.
Figure 18.2 Data Format Used by the Smart Card Interface
Ds
D0 to D7
Dp
DE
When a parity error occurs in T=1 mode
When a parity error occurs in T=0 mode
When no parity error occurs
Ds
Ds
Ds
Ds
Ds
: Start bit
: Data bits
: Parity bit
: Error signal
D0
D0
D0
D1 D2
D1
D1
D2
Transmitter output
Transmitter output
Transmitter output
D2
D3
D3
D3
D4
D4
D4
D5 D6
D5
D5 D6 D7
D6
D7 Dp
D7
Dp
Dp
Receiver output
DE

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