HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 195

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Category
Graphics
acceleration
instructions
Notes: 1. See table 5.1 for the instruction groups.
Exceptions:
Functional
2. Latency "L1/L2... ": Latency corresponding to a write to each register, including
3. Branch latency: Interval until the branch destination instruction is fetched
4. Conditional branch latency "2 (or 1) ": Latency is 2 for a non-zero displacement, and 1
5. Double-precision floating-point instruction latency " (L1, L2)/L3": L1 is the latency for FR
6. FTRV latency " (L1, L2, L3, L4)/L5": L1 is the latency for FR [n], L2 that for FR [n+1], L3
7. Latency "L1/L2/L3/L4" of MAC.L and MAC.W instructions: L1 is the latency for Rm, L2
8. Latency "L1/L2" of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.L instructions:
9. Execution pattern: Instruction execution pattern number (see figure 5.2)
10. Lock/stage: Stage locked by the instruction
11. Lock/start: Locking start cycle; 1 is the first D-stage of the instruction.
12. Lock/cycles: Number of cycles locked
1. When a floating-point computation instruction is followed by an FMOV store instruction,
2. When the preceding instruction loads the shift amount of the following SHAD/SHLD,
3. When an LS group instruction with latency of less than 3 cycles is followed by a double-
4. When MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L is followed by an
MACH/MACL/FPSCR.
Example: MOV.B @Rm+, Rn "1/2": Latency for Rm is 1 cycle and latency for Rn is 2
for a zero displacement.
[n+1], L2 that for FR [n], and L3 that for FPSCR.
that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR.
that for Rn, L3 that for MACH, and L4 that for MACL.
L1 is the latency for MACH, and L2 that for MACL.
an STS FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, latency of the
floating-point computation is decreased by 1 cycle.
latency of the load is increased by 1 cycle.
precision floating-point instruction, FIPR, or FTRV, latency of the first instruction is
increased to 3 cycles.
Example: In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2
STS.L MACH/MACL, @-Rn instruction, latency of MAC.W/MAC.L/MUL.L/MULS.W/
MULU.W/DMULS.L/DMULU.L is 5 cycles.
233
No.
231
232
234
FSCHG
Instruction
FIPR
FRCHG
FTRV
cycles.
cycles.
FVm,FVn
XMTRX,FVn
FE
Instruc-
tion
Group
FE
FE
FE
1
Issue
Rate
1
1
1
Rev. 2.00 Feb. 12, 2010 Page 111 of 1330
Latency
4/5
1/4
(5, 5,
6, 7)/8
1/4
Execution
Pattern
#42
#36
#36
#43
Stage Start Cycles
F1
—
—
F0
F1
REJ09B0554-0200
3
—
2
3
—
Lock
—
1
—
4
4