HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 490

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.3.7
Refer to section 24.2.34, DMA Pin Control Register (DMAPCR), in section 24, Pin Function
Controller (PFC) for details regarding DMAPCR.
11.3.8
DMARCR is a 32-bit readable/writable register that switches between DRAK2 and DACK2 and
between DRAK3 and DACK3 in DMABRG mode, selects the interrupt level for DRAK and
DACK, detects DREQ0 to DREQ3, and specifies the acceptance priority of requests from DREQ0
to DREQ3 and DMABRG. The numbers 0, 1, 2, and 3 in the bit names of DS, RL and AL
correspond to DREQ0, DREQ1, DREQ2, and DREQ3 (channel numbers are not indicated). This
DMARCR setting is invalid in external request 2-channel mode.
Initial value:
Initial value:
Bit
31
30
29
28
27
Rev. 2.00 Feb. 12, 2010 Page 406 of 1330
REJ09B0554-0200
R/W:
R/W:
Bit:
Bit:
DMA Pin Control Register (DMAPCR)
DMA Request Control Register (DMARCR)
Bit Name
REX7
REX6
REX5
REX4
REX3
REX7 REX6
31
15
R
R
0
0
-
DS3
R/W
30
14
0
R
0
REX5
RL3
R/W
29
13
0
R
0
Initial Value
0
0
0
0
0
REX4 REX3
AL3
R/W
28
12
0
R
0
27
11
0
R
0
R
-
REX2
DS2
R/W
26
10
R
0
0
R/W
R
R
R
R
R
REX1
RL2
R/W
25
0
R
9
0
Description
Channel 7 Request Reception*
0: Channel 7 does not accept a transfer request
1: Channel 7 accepts a transfer request
Channel 6 Request Reception*
0: Channel 6 does not accept a transfer request
1: Channel 6 accepts a transfer request
Channel 5 Request Reception*
0: Channel 5 does not accept a transfer request
1: Channel 5 accepts a transfer request
Channel 4 Request Reception*
0: Channel 4 does not accept a transfer request
1: Channel 4 accepts a transfer request
Channel 3 Request Reception*
0: Channel 3 does not accept a transfer request
1: Channel 3 accepts a transfer request
REX0
AL2
R/W
24
0
R
0
8
R/A3
R/W
23
0
7
0
R
-
R/A2
R/W
DS1
R/W
22
0
6
0
RL1
R/W
21
R
0
5
0
-
AL1
R/W
20
R
0
4
0
-
19
R
R
0
3
0
-
-
4
4
4
4
4
*
*
*
*
*
7
7
7
7
7
DS0
R/W
18
2
-
0
R
0
RPR1 RPR0
R/W
RL0
R/W
17
0
1
0
R/W
R/W
AL0
16
0
0
0