HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 239

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Cache control register
Queue address control register 0
Queue address control register 1
Register Name
• Data array
• LRU
7.2
The following registers are related to cache. For details on the addresses of these registers and the
state of registers in each operating mode, see section 32, List of Registers.
Table 7.4
Register Name
Cache control register
Queue address control register 0
Queue address control register 1
Table 7.4
Note:
Memory-Mapped Cache Configuration (Cache Direct Mapping Mode)). The U bit is initialized
to 0 by a power-on reset, but retains its value in a manual reset.
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
In a 2-way set-associative method, up to 2 items of data can be registered in the cache at each
entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be
registered in. The LRU bit is a single bit of each entry, and its usage is controlled by hardware.
The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently
accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset.
The LRU bits cannot be read from or written to by software.
* After exiting hardware standby mode, this LSI enters the power-on reset state caused
Register Descriptions
by the RESET pin.
Register Configuration (1)
Register Configuration (2)
CCR
QACR0
QACR1
Abbrev.
Abbrev.
CCR
QACR0
QACR1
Undefined
Undefined
Power-on Reset
by RESET
Pin/WDT/H-UDI
H'0000 0000
R/W
R/W
R/W
R/W
P4 Address
H'FF00 001C
H'FF00 0038
H'FF00 003C
H'0000 0000
Undefined
Undefined
Manual Reset by
RESET Pin/WDT/
Multiple
Exception
Rev. 2.00 Feb. 12, 2010 Page 155 of 1330
Area 7 Address
H'1F00 001C
H'1F00 0038
H'1F00 003C
Retained
Retained
Retained
Sleep
by Sleep
Instruction/
Deep Sleep
by
Hardware
REJ09B0554-0200
Size
32
32
32
*
Standby
Retained
Retained
Retained
by
Software/
Each
Module
Sync
Clock
Ick
Ick
Ick