HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 406

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

between the Tr cycle and the Tc cycle. Bits A2W2 to A2W0 and A3W2 to A3W0 in WCR2 can be
used to specify the number of cycles from READ command output cycle Tc1 to the first read data
latch cycle Td1 as 1 to 5 cycles independently for areas 2 and 3. This number of cycles
corresponds to the number of synchronous DRAM CAS latency cycles.
DACKn
(SA: IO ← memory)
In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the beginning of each
data transfer cycle corresponding to a READ or READA command. When the data is accessed in
the fill operation for a cache miss, the 64-bit boundary data including the missing data are first
read by the initial READ command, and then the 16-byte boundary data including the missing
data are read in wraparound mode. READA commands that are subsequently issued are used to
read the 16 bytes of data, which is the remainder of the 32-byte boundary data.
Rev. 2.00 Feb. 12, 2010 Page 322 of 1330
REJ09B0554-0200
CKIO
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
BS
CKE
Bank
D31–D0
(read)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.16 Basic Timing for Synchronous DRAM Burst Read
Tr
Row
Row
Row
Trw
Tc1
c1
H/L
Tc2
Tc3 Tc4/Td1
c1
Td2
H/L
c5
c2
Td3
c3
Td4
c4
Td5
c5
Td6
c6
Td7
c7
Td8
c8
Tpc