HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 736

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.4.4
(1) Initialization
Prior to data transmission and reception, the procedure shown in figure 18.4 should be used to
initialize the smart card interface. Initialization is also necessary when switching from transmitter
mode to receiver mode, and when switching from receiver mode to transmitter mode. An example
of the initialization process is shown in the flow chart of figure 18.4.
Rev. 2.00 Feb. 12, 2010 Page 652 of 1330
REJ09B0554-0200
Set SIBRR, SISMPL, SIWAIT, and SIGRD
Set the clock using the CKE1 and CKE0
Set the parity using the O/E bit in SISMR
TE, RE, TEIE and WAIT_IE flags to 0.
Data Transmission/Reception Operation
bits in SISCR. Clear the TIE, RIE,
Clear the TE, RE bits in SISCR to 0
Set the LCB, PB, SMIF, SDIR, and
Set the TIE, RIE, TE, RE, TEIE,
Clear the ERS, PER, ORER, and
and WAIT_IE bits in SISCR
WAIT_ER flags in SISSR to 0
SINV bits in SISCMR
interval elapsed?
Initialization
Has a 1-bit
End
Yes
Figure 18.4 Example of Initialization Flow
Wait
No
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Clear the TE and RE bits in SISCR to 0.
Clear the error flags PER, ORER, ERS, and
WAIT_ER in SISSR to 0.
Set the parity bit (O/E bit) in SISMR.
Set the LCB, PB, SMIF, SDIR, and SINV bits in
SISCMR.
Set the value corresponding to the bit rate in
SIBRR.
Set SISMPL, SIWAIT, SIGRD.
Set the clock source select bits (CKE1, CKE0)
in SISCR. At this time, the TIE, RIE, TE, RE,
TEIE, and WAIT_IE bits are set to 0.
If the CKE0 bit is set to 1, a clock signal is
output from the SIM_CLK pin.
After waiting at least 1 etu, set the TIE, RIE,
TE, RE, TEIE, and WAIT_IE bits in SISCR.