HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 906

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Rev. 2.00 Feb. 12, 2010 Page 822 of 1330
REJ09B0554-0200
Bit
3
2
1
Bit Name
IRR3
IRR2
IRR1
Initial Value
0
0
0
R/W
R/W
R
R
Description
Transmit Overload Warning Interrupt Flag
This bit becomes set and latches if the transmit
error counter (TEC) reaches a value greater than
96. This bit is cleared by writing a 1. Writing a 0
has no effect. When the interrupt is cleared, the
TEC still holds a value greater than 96.
0: Clearing condition: Write a 1 to this bit.
1: Error warning state is caused by a transmit
Remote Frame Request Interrupt Flag
Indicates that a Remote Frame has been received
in a Mailbox. This bit is set if at least one receive
mailbox contains a Remote Frame transmission
request. This bit is cleared by ensuring all bits in
the Remote Request Pending Register
(CANRFPR) are cleared. Writing to this bit has no
effect.
0: Clearing condition: Clearing all bits in
1: At least one remote request is pending
Data Frame Received Interrupt Flag
Indicates that there is a pending Data Frame
received. If this bit is set at least on receive
mailbox contains a pending message. This bit is
cleared when all bits in the Receive Message
Pending Register (CANRXPR) are cleared, i.e.
there is no pending message in any receiving
mailbox. It is a logical OR from each configured
receive mailbox. Writing to this bit has no effect.
0: Clearing condition: Clearing all bits in
1: Data Frame is received and stored in Mailbox
error. Setting condition: TEC ≥ 96
CANRFPR.
Setting conditions: When remote frame is
received and the corresponding CANMBIMR =
0.
CANRXPR.
Setting conditions: When data is received and
the corresponding CANMBIMR = 0.

Related parts for HD6417760BL200AV