HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 709

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Thus, the reception margin in asynchronous mode is given by formula (1).
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L:
F:
From equation (1), if F = 0 and D = 0.5, the reception margin is 46.875%, as given by formula (2).
When D = 0.5 and F = 0:
However, this is a theoretical value. A reasonable margin to allow in system designs is 20% to
30%.
Frame length (L = 9 to 12)
Absolute value of clock rate deviation
Synchronization
sampling timing
Data sampling
Receive data
M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ......................................................... (2)
M= (0.5 -
(SCIF_RXD)
Base clock
Figure 17.22 Receive Data Sampling Timing in Asynchronous Mode
timing
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
2N
1
Start bit
8 clocks
) - (L - 0.5) F -
16 clocks
–7.5 clocks
| D - 0.5 |
N
+7.5 clocks
(1 + F) × 100 % .................... (1)
Rev. 2.00 Feb. 12, 2010 Page 625 of 1330
D0
REJ09B0554-0200
D1