HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 464

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 11.1 shows a block diagram of the DMAC.
Rev. 2.00 Feb. 12, 2010 Page 380 of 1330
REJ09B0554-0200
Legend:
1. This unit has the following 55 registers.
DMAOR
SAR 0 to 7
DAR 0 to 7
DMATCR 0 to 7
CHCR 0 to 7
DMARSRA
DMARSRB
DMAPCR
The following registers are valid only in DMABRG mode.
DMABRGCR
DMAATXSAR 0 and 1
DMAARXDAR 0 and 1
DMAATXTCR 0 and 1
DMAARXTCR 0 and 1
DMAACR0 and 1
DMAATXTCNT 0 and 1
DMAARXTCNT 0 and 1
DMAUSAR
DMAUDAR
DMAURWSZ
DMAUCR
DMARCR
peripheral
module*
On-chip
DREQn*
DRAKn*
DACKn*
2
3
3
3
32-byte data
Bus state
controller
: DMA operation register
: DMA source address registers 0 to 7
: DMA destination address registers 0 to 7
: DMA transfer count registers 0 to 7
: DMA channel control registers 0 to 7
: DMA request resource selection register A
: DMA request resource selection register B
: DMA pin control register
: DMA BRG control register
: DMA audio source address registers 0 and 1
: DMA audio destination address registers 0 and 1
: DMA audio transmit transfer count registers 0 and 1
: DMA audio receive transfer count registers 0 and 1
: DMA audio control registers 0 and 1
: DMA audio transmit transfer counters 0 and 1
: DMA audio receive transfer counters 0 and 1
: DMA USB source address registers 0 to 7
: DMA USB destination address register
: DMA USB R/W size register
: DMA USB control register
: DMA request control register
buffer
Figure 11.1 DMAC Block Diagram
peripheral module address
External address/on-chip
acceptance control
Activation control
Transfer request
Transfer request
Bus interface
Register control
priority control
Count control
External bus
2.
3. n = 0 to 3
The following 14 on-chip peripheral modules can
output DMA transfer requests.
SCIF 0 to 2
HSPI
SIM
MMCIF
ADC
The following modules can output DMA transfer
requests to the DMABRG.
LCDC
HAC 0 and 1
SSI 0 and 1
USB
DMAC module
: Serial communication interface 0 to 2
: Serial peripheral interface
: Smartcard interface
: Multimedia card interface
: A/D converter
: LCD controller
: Audio codec interface 0 and 1
: Serial sound interface 0 and 1
: USB host
register
DMABRG
DMAC
unit*
1