HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 231

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.6.5
UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to data array 1
are specified in the data field.
In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1 and the entry
is specified by bits [13:8].
In the data field, bits [28:10] indicate PPN, bit [8] indicates V, bits [7] and [4] indicate SZ, bits
[6:5] indicate PR, bit [3] indicates C, bit [2] indicates D, bit [1] indicates SH, and bit [0] indicates
WT.
When a write is performed with the A bit in the address field set to 1, comparison of all the
UTLB entries is carried out using the VPN specified in the data field and ASID in PTEH. The
usual address comparison rules are followed, but if a UTLB miss occurs, the result is no
operation, and an exception is not generated. If the comparison identifies a UTLB entry
corresponding to the VPN specified in the data field, D and V specified in the data field are
written to that entry. If there is more than one matching entry, a data TLB multiple hit
exception occurs. This associative operation is simultaneously carried out on the ITLB, and if a
matching entry is found in the ITLB, V is written to that entry. Even if the UTLB comparison
results in no operation, a write to the ITLB side only is performed as long as there is an ITLB
match. If there is a match in both the UTLB and ITLB, the UTLB information is also written to
the ITLB.
UTLB Data Array 1
Address field
Data field
Figure 6.15 Memory-Mapped UTLB Address Array
31
31
1 1 1 1 0 1 1 0
VPN:
D:
V:
E:
Virtual page number
Validity bit
Entry
Dirty bit
24
23
VPN
ASID:
A:
:
Address space identifier
Association bit
Reserved bits (write value should be 0,
and read value is undefined )
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E
10 9 8 7
D
8 7
V
A
6
ASID
REJ09B0554-0200
0
0