HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 605

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14.3.4
(1) Transition to Module Standby Function
Setting 1 to the MSTP6 to MSTP4 and MSTP2 bits in STBCR and STBCR2, and the CSTP31 to
CSTP0 bits in CLKSTP00 enables the clock supply to the corresponding peripheral modules to be
halted. Use of this function allows power consumption in sleep mode to be further reduced.
In the module standby state, the peripheral module external pins retain their states prior to halting
of the modules, and most registers retain their states prior to halting of the modules.
(2) Exit from Module Standby Function
In the case of STBCR and STBCR2, the module standby function is exited by writing 0 to the
MSTP6 to MSTP4 and MSTP2 bits. In the case of CLKSTP00, the module standby function is
exited by writing 1 to the corresponding bit in CLKSTPCLR00.
The module standby function is also exited by means of a power-on reset via the RESET pin or a
power-on reset caused by watchdog timer overflow.
14.3.5
(1) Transition to Hardware Standby Mode
Setting the CA pin level low effects a transition to hardware standby mode. Note that the CA pin
must be continuously held low while in hardware standby mode. In this mode, all modules stop, as
in software standby mode selected using the SLEEP instruction.
Hardware standby mode differs from software standby mode in the following points:
(a) Interrupts and manual resets are not available.
(b) All output pins other than the STATUS pins are in the high-impedance state and the pull-up
Operation when a low-level is input to the CA pin in software standby mode depends on the CPG
status, as follows:
(a) In software standby mode
(b) When WDT is operating at the time software standby mode is exited by interrupt
resistance is off.
After software standby mode is momentarily exited and the CPU restarts operation, a transition
is made to hardware standby mode.
The clock remains stopped and a transition is made to the hardware standby state.
Module Standby Function
Hardware Standby Mode
Rev. 2.00 Feb. 12, 2010 Page 521 of 1330
REJ09B0554-0200