HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 480

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
3
2
1
Rev. 2.00 Feb. 12, 2010 Page 396 of 1330
REJ09B0554-0200
Bit Name
CHSET
IE
TE
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Channel Setting
Since the internal state of the acceptance unit for
the corresponding channel external and DMABRG
requests are cleared when 1 is written to this bit in
DMABRG mode, write 1 to this bit when setting up
the corresponding channel. Note, however, that
this bit always reads out as 0.
Note: This operation is invalid in external request
Interrupt Enable
When this bit is set to 1, an interrupt request
(DMTE) is generated after completing a number of
data transfers specified in DMATCR (when TE =
1). When a DMABRG request DMA transfer is
executed in DMABRG mode, the DMTE0 signal
cannot be generated.
0: Interrupt request is not generated after
1: Interrupt request is generated after completing a
Transfer End
This bit is set to 1 after the number of transfers
specified in DMATCR. If the IE bit is set to 1 at this
time, an interrupt request (DMTE) is generated.
If data transfer ends before this bit is set to 1 due
to an NMI interrupt, address error, or clearing of
the DE bit or the DME bit in DMAOR, etc., this bit
is not set to 1. When this bit is 1, the transfer
enabled state is not entered even if the DE bit is
set to 1.
0: Number of transfers specified in DMATCR not
[Clearing condition]
When 0 is written to TE after reading TE = 1
1: Number of transfers specified in DMATCR
completed
completing a number of transfers specified in
DMATCR
number of transfers specified in DMATCR
completed
2-channel mode.