HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 419

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

addresses in the same bank, the PRE command cannot be issued until one cycle before the last
data latch cycle. If a write access follows a read access, a PRE or ACTV command can be issued
depending on the bank and row address, but since the write data is output at the same time as the
WRIT command, the PRE, ACTV, and WRIT commands are issued so that one or two dummy
cycles occur automatically on the data bus. Similarly, when a read access follows a write access,
or a write access follows a write access, the PRE, ACTV, or READ command is issued during the
data write cycle for the preceding access. However, a PRE command cannot be issued for different
row addresses in the same bank, and so the PRE command is issued following the number of Trwl
cycles specified by the TRWL bit in MCR after the end of the last data write cycle.
Figure 10.26 shows a burst read cycle for different banks and row addresses from the preceding
burst read cycle.
Pipelined access is enabled only for consecutive access to area 3, and is aborted when there is an
access to another area. Pipelined access is also aborted in the event of a refresh cycle, or bus
release due to bus arbitration. The cases where pipelined access is available are shown in table
10.17. In this table, DMAC dual indicates transfer by DMAC dual address mode, and DMAC
single indicates transfer by DMAC single address mode.
Address
CKIO
Bank
Precharge-sel
CSn
RD/WR
RAS
CASS
DQMn
BS
CKE
D31-D0
(read)
Figure 10.26 Burst Read Cycle for Different Bank and Row Address From Preceding Burst
Tc1_A
c1_A
H/L
a1
c5_A
Read Cycle
H/L
a2
a3
a4
Rev. 2.00 Feb. 12, 2010 Page 335 of 1330
a5
Tc1_B
c1_B
H/L
a6
a7
a8
REJ09B0554-0200
b1
c5_B
H/L
b2