HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 182

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The instruction execution sequence is expressed as a combination of the execution patterns shown
in figure 5.2. One instruction is separated from the next by the number of machine cycles for its
issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the
same stages of another instruction; the only exception is when two instructions are executed in
parallel under parallel-executability conditions. See (a) to (d) in figure 5.3 for some simple
examples.
Latency is the interval between issue and completion of an instruction, and is also the interval
between the execution of two instructions with an interdependent relationship. When there is
interdependency between two instructions fetched simultaneously, the latter of the two is stalled
for the following number of cycles:
• (Latency) cycles when there is flow dependency (read-after-write)
• (Latency − 1) or (latency − 2) cycles when there is output dependency (write-after-write)
• Five or two cycles when there is anti-flow dependency (write-after-read), as in the following
In the case of flow dependency, the latency may be exceptionally increased or decreased,
depending on the combination of sequential instructions (figure 5.3 (e)).
• When a floating-point computation is followed by a floating-point register store, latency of the
• If there is a load of the shift amount immediately before an SHAD or SHLD instruction,
• If an instruction with latency of less than two cycles, including write-back to a floating-point
The number of cycles in a pipeline stall due to flow dependency will vary depending on the
combination of interdependent instructions or the fetch timing (see figure 5.3 (e)).
Output dependency occurs when the destination operands are the same in a preceding FE group
instruction and a following LS group instruction.
For the stall cycles of an instruction with output dependency, the longest latency to the last write-
back among all the destination operands must be applied instead of "latency" (see figure 5.3 (f)). A
stall due to output dependency with respect to FPSCR, which reflects the result of a floating-point
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⎯ Single/double-precision FDIV or FSQRT is the preceding instruction: (latency – 1) cycles
⎯ Other instructions in the FE group is the preceding instruction: (latency – 2) cycles
cases:
⎯ FTRV is the preceding instruction: 5 cycles
⎯ Double-precision FADD, FSUB, or FMUL is the preceding instruction: 2 cycles
floating-point computation may be decreased by one cycle.
latency of the load is increased by one cycle.
register, is followed by a double-precision floating-point instruction, FIPR, or FTRV, latency
of the first instruction is increased to two cycles.