HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 201

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues
(SQs). When the MMU is disabled (AT bit in MMUCR = 0), the SQ access right is specified by
the SQMD bit in MMUCR. For details, see section 7.7, Store Queues.
The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache
address array. For details, see section 7.6.1, IC Address Array.
The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data
array. For details, see section 7.6.2, IC Data Array.
The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB
address array. For details, see section 6.6.1, ITLB Address Array.
The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data
arrays 1 and 2. For details, see section 6.6.2, ITLB Data Array 1, and section 6.6.3, ITLB Data
Array 2.
The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address
array. For details, see section 7.6.3, OC Address Array.
H'E000 0000
H'E400 0000
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
H'F500 0000
H'F600 0000
H'F700 0000
H'F800 0000
H'FC00 0000
H'FFFF FFFF
Figure 6.3 P4 Area
Instruction TLB data arrays 1 and 2
Unified TLB data arrays 1 and 2
Instruction cache address array
Operand cache address array
Instruction TLB address array
Instruction cache data array
Operand cache data array
Unified TLB address array
Control register area
Reserved area
Reserved area
Store queue
Rev. 2.00 Feb. 12, 2010 Page 117 of 1330
REJ09B0554-0200