HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 788

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 I
19.7.2
There are restrictions on the timing with which FSB may be set during I²C bus interface FIFO
buffer mode master transmission.
When a stop condition (P) is issued in FIFO buffer mode, that stop condition (P) may not be
issued correctly if the timing with which FSB is set to 1 meets either of the conditions (1) or (2)
below.
(1) If that setting occurs during or before the transmission of the last bit (bit 8) of the next to last
(2) If that setting occurs during or after the transmission of the last bit of the last data item (data
If FSB is set to one with the above timing, in case (1) the stop condition (P) may be issued after
the transmission of data item (n-1) and data item n may not be issued. Also, in case (2), a stop
condition (P) may not be issued after transmission of data item n.
• Software Workaround
Rev. 2.00 Feb. 12, 2010 Page 704 of 1330
REJ09B0554-0200
In master transmitter mode, the software checks the MST (transmission end) bit by interrupt or
polling after the last byte is set. At the same time, it checks MNR (master NACK received). If
NACK is returned, it makes a branch to the error routine where the last byte is retransmitted.
In master receiver mode, the software ends reception after confirming that the last byte has
been received. However, if the last byte has any defect, it issues a retransmission request by
the upper protocol.
data item (data item (n-1)).
item n).
Set FSB to 1 after the last bit of data item (n-1), and before the last bit of data item n, has been
transmitted. In particular, as shown in the figure 19.11, set FSB within the 8 SCL clock cycle
period following one clock SCL cycle after TDFE is set to 1 ((1) in the figure) and through the
ninth SCL clock cycle after that setting ((2) in the figure).
Restriction 2
2
C Bus Interface