HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1222

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3. Operand access match on channel A, instruction access match on channel B
4. Operand access matches on both channel A and channel B
31.4
1. Do not execute a post-execution instruction access break for the SLEEP instruction.
2. Do not make an operand access break setting between 1 and 3 instructions before a SLEEP
3. The value of the BL bit referenced in a user break exception depends on the break setting, as
Rev. 2.00 Feb. 12, 2010 Page 1138 of 1330
REJ09B0554-0200
Instruction B is 0 to 3 instructions after
instruction A
Instruction B is 4 or more instructions
after instruction A
Do not make a setting such that a single operand access will match the break conditions of
both channel A and channel B. There are no other restrictions. For example, sequential
operation is guaranteed even if two accesses within a single instruction match channel A and
channel B conditions in turn.
instruction.
follows.
⎯ Pre-execution instruction access break: The BL bit value before the executed instruction is
⎯ Post-execution instruction access break: The OR of the BL bit values before and after the
⎯ Operand access break (address/data): The BL bit value after the executed instruction is
⎯ In the case of an instruction that modifies the BL bit
referenced.
executed instruction is referenced.
referenced.
BL bit
0 → 0
1 → 0
0 → 1
1 → 1
A: Accepted
M: Masked
Usage Notes
Pre-
Execution
Instruction
Access
A
M
A
M
Post-
Execution
Instruction
Access
A
M
M
M
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Pre-
Execution
Instruction
Access
A
M
A
M
Post-
Execution
Instruction
Access
A
M
M
M
Operand Access
(Address/Data)
A
A
M
M