HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 127

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2.2.2
Figure 2.3 shows the relationship between the processing modes and general registers. The SH-4
has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to
R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0
to R15 in one processing mode. The SH-4 has two processing modes, user mode and privileged
mode.
• R0_BANK0 to R7_BANK0
• R0_BANK1 to R7_BANK1
Allocated to R0 to R7 in user mode (SR.MD = 0)
Allocated to R0 to R7 when SR.RB = 0 in privileged mode (SR.MD = 1).
Cannot be accessed in user mode.
Allocated to R0 to R7 when SR.RB = 1 in privileged mode.
Note :
General Registers
As the user's R0-R7 are assigned to R0_BANK0-R7_BANK0, and after an exception or interrupt R0-R7
are assigned to R0_BANK1-R7_BANK1, it is not necessary for the interrupt handler to save and restore
the user's R0-R7 (R0_BANK0-R7_BANK0).
After a reset, the values of R0_BANK0-R7_BANK0, R0_BANK1-R7_BANK1, and R8-R15 are undefined.
SR.MD = 0 or
(SR.MD = 1, SR.RB = 0)
R0 _ BANK1
R1 _ BANK1
R2 _ BANK1
R3 _ BANK1
R4 _ BANK1
R5 _ BANK1
R6 _ BANK1
R7 _ BANK1
R10
R11
R12
R13
R14
R15
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Figure 2.3 General Registers
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
R0_BANK1
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
R10
R11
R12
R13
R14
R15
R8
R9
R0
R1
R2
R3
R4
R5
R6
R7
R10
R11
R12
R13
R14
R15
(SR.MD = 1, SR.RB = 1)
R0 _ BANK0
R1 _ BANK0
R2 _ BANK0
R3 _ BANK0
R4 _ BANK0
R5 _ BANK0
R6 _ BANK0
R7 _ BANK0
R8
R9
Rev. 2.00 Feb. 12, 2010 Page 43 of 1330
REJ09B0554-0200