HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 149

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.7.3
When two or more data items used in an operation by the FIPR or FTRV instruction are infinity,
and all of the infinity items in the multiplication results have the same sign, the sign of the
operation result may be incorrect.
Workarounds
1. Do not use infinity. If conditions (a) to (c) below are satisfied, infinity is never used in
2. Avoid using the FIPR and FTRV instructions, and use the FADD, FMUL, and FMAC
3.7.4
Description: If the input data for a double-precision FADD instruction or a double-precision
FSUB instruction satisfies all of the conditions listed below, the inexact bits (FPSCR.Flag.I and
FPSCR.Cause.I) may not be set even through the operation result is inexact.
Condition 1: The operation instruction is a double-precision FADD instruction or a double-
Condition 2: The difference between the DRn and DRm exponents is between 43 and 50.
Condition 3: At least one of bits 31 to 24 of the mantissa portion of whichever of DRn and DRm
Condition 4: Bits 23 to 0 of the mantissa portion of whichever of DRn and DRm has the smaller
Condition 5: Bits 40 to 32 of the mantissa portion of whichever of DRn and DRm has the smaller
In addition, the result of an operation meeting the above conditions may have a rounding error.
Specifically, in a case where the closest expressible value less than the unrounded value should be
selected, the closest expressible value greater than the unrounded value is selected instead.
Conversely, in a case where the closest expressible value greater than the unrounded value should
be selected, the closest expressible value less than the unrounded value is selected instead.
operations.
a. Use Round to Zero (FPSCR.RM = 01) as the rounding mode.
b. Do not divide by zero.
c. Do not transfer a value of positive or negative infinity to FR0 to FR15 or to XF0 to XF15.
instructions instead.
Notes on Double-Precision FADD and FSUB Instructions
Sign of Operation Result when Using FIPR or FTRV Instruction
precision FSUB instruction.
has the smaller absolute value is 1.
absolute value are all 0.
absolute value are all 0.
Rev. 2.00 Feb. 12, 2010 Page 65 of 1330
REJ09B0554-0200