HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 184

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 100 of 1330
REJ09B0554-0200
(a) Serial execution: Non-parallel-executable instructions
(b) Parallel execution: Parallel-executable and no dependency
(c) Issue rate: Multi-step instruction
(d) Branch
SHAD R0,R1
ADD
next
ADD
MOV.L @R4,R5
AND.B#1,@(R0,GBR)
MOV
next
BT/S L_far
ADD R0,R1
SUB R2,R3
BT/S L_far
ADD R0,R1
L_far
BT L_skip
ADD #1,R0
L_skip:
R2,R3
R2,R1
R1,R2
I
I
I
I
I
I
I
I
I
I
I
I
Figure 5.3 Examples of Pipelined Execution
No stall
4 stall cycles
D
D
D
D
D
D
D
D
D
D
I
I
I
1 stall cycle
1 issue cycle
1 issue cycle
2-cycle latency for I-stage of branch destination
1 stall cycle
EX
EX
EX
SX
EX
EX
EX
EX
EX
D
D
D
D
—
D
I
...
...
NA
EX
NA
MA
MA
SX
EX
NA
NA
NA
NA
NA
—
D
D
...
NA
NA
SX
NA
—
D
S
S
S
S
S
S
S
S
S
I
i
4 issue cycles
...
SX
NA
D
S
S
S
MA
E
S
S
A
EX-group SHAD and EX-group ADD
cannot be executed in parallel. Therefore,
the preceding SHAD is issued, and the
following ADD is recombined with the next
instruction.
EX-group ADD and LS-group MOV.L can
be executed in parallel. Overlapping of
stages in the two instructions is possible.
AND.B and MOV are fetched
simultaneously, but MOV is stalled due to
resource locking. After the lock is released,
MOV is refetched together with the next
instruction.
No stall occurs if the branch is not taken.
If the branch is taken, the I-stage of the
branch destination is stalled for the period
of latency. This stall can be covered with a
delay slot instruction which is not parallel-
executable with the branch instruction.
Even if the BT/BF branch is taken, the I-
stage of the branch destination is not
stalled if the displacement is zero.
S