HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1209

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
31.2.3
BAMRA is an 8-bit readable/writable register that specifies which bits are to be masked in the
break ASID set in BASRA and the break address set in BARA.
Note: x: Don't care
Bit
7 to 4
2
3
1
0
Break Address Mask Register A (BAMRA)
Bit Name
BASMA
BAMA2
BAMA1
BAMA0
Initial value:
Initial Value
All 0
R/W:
Bit:
7
R
0
-
R
6
0
-
R/W
R
R/W
R/W
R/W
R/W
R
5
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Break ASID Mask A
Specifies whether all bits of the channel A break
ASID (BASA7 to BASA0) set in BASRA are to be
masked.
0: All BASRA bits are included in break conditions
1: No BASRA bits are included in break conditions
Break Address Mask A2 to A0
These bits specify which bits of the channel A
break address (BAA31 to BAA0) set in BARA are
to be masked.
000: All BARA bits are included in break conditions
001: Lower 10 bits of BARA are masked, and not
010: Lower 12 bits of BARA are masked, and not
011: All BARA bits are masked, and not included in
100: Lower 16 bits of BARA are masked, and not
101: Lower 20 bits of BARA are masked, and not
11x: Setting prohibited
R
4
0
-
included in break conditions
included in break conditions
break conditions
included in break conditions
included in break conditions
BAMA2 BASMA BAMA1 BAMA0
R/W
3
-
Rev. 2.00 Feb. 12, 2010 Page 1125 of 1330
R/W
2
-
R/W
1
-
R/W
0
-
REJ09B0554-0200

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