HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 203

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

When the P0, P3, and U0 areas are mapped onto a PCMCIA interface area by means of the TLB in
the cache enabled state, either the WT bit in CCR must be set to 1 or the C bit in PTEL must be
cleared to 0 for that page. In this case, access to the area is performed using the SA and TC bit
values specified in page units for each TLB page.
Note that the CPU cannot access a PCMCIA interface area through access of the P1, P2, or P4
area. Access to a PCMCIA interface area by the DMAC is always performed using the SSAn,
DSAn, STC, and DTC values in CHCRn of the DMAC. For details, see section 11, Direct
Memory Access Controller (DMAC).
P0, P3, and U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area,
and U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and
address translation using the TLB. These areas can be mapped onto any external memory space in
1-, 4-, or 64-Kbyte, or 1-Mbyte page units. When CCR is in the cache enabled state and the TLB
cacheability bit (C bit) is 1, accesses can be performed using the cache. In write accesses to the
cache, switching between the copy-back method and the write-through method is indicated by the
TLB write-through bit (WT bit), and is specified in page units.
256
Address translation not possible
Address translation not possible
Address translation not possible
Address translation possible
Address translation possible
Privileged mode
Non-cacheable
Non-cacheable
Cacheable
Cacheable
Cacheable
Figure 6.5 Virtual Address Space (AT = 1 in MMUCR)
P0 area
P1 area
P2 area
P3 area
P4 area
memory space
External
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
256
Rev. 2.00 Feb. 12, 2010 Page 119 of 1330
Address translation possible
Store queue area
Address error
Address error
User mode
Cacheable
U0 area
REJ09B0554-0200