HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 243

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.2.3
QACR1 can be accessed in longwords from H'FF00 003C in the P4 area and from H'1F00 003C in
area 7. QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is
off.
Initial value:
Initial value:
7.3
7.3.1
When the OC is enabled (OCE = 1 in CCR) and data is read by means of an effective address from
a cacheable area, the cache operates as follows:
1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
Bit
31 to 5
4 to 2
1, 0
translation by the MMU:
• If the tag matches and the V bit is 1
• If the tag matches and the V bit is 0
• If the tag does not match and the V bit is 0
• If the tag does not match, the V bit is 1, and the U bit is 0 → 4.
• If the tag does not match, the V bit is 1, and the U bit is 1 → 5.
R/W:
R/W:
Bit:
Bit:
Queue Address Control Register 1 (QACR1)
Operand Cache Operation
Read Operation
Bit Name
⎯
AREA1
⎯
31
15
R
R
-
-
-
-
30
14
R
R
-
-
-
-
29
13
R
R
-
-
-
-
Initial Value
⎯
⎯
⎯
28
12
R
R
-
-
-
-
27
11
R
R
-
-
-
-
26
10
R
R
-
-
-
-
R/W
R
R/W
R
25
R
R
9
-
-
-
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
When the MMU is off, these bits generate external
address bits [28:26] for SQ1.
Reserved
These bits are always read as 0. The write value
should always be 0.
24
R
R
8
-
-
-
-
23
R
R
7
-
-
-
-
Rev. 2.00 Feb. 12, 2010 Page 159 of 1330
22
R
R
6
-
-
-
-
→ 3.
→ 4.
→ 4.
21
R
R
5
-
-
-
-
R/W
20
R
4
-
-
-
AREA1
R/W
19
R
3
-
-
-
REJ09B0554-0200
R/W
18
R
-
-
2
-
17
R
R
1
-
-
-
-
16
R
R
-
-
0
-
-