HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 433

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SA2
0
1
When the MMU is on, wait cycles in a bus access can be set in MMU page units. For details of the
setting method, see section 6, Memory Management Unit (MMU). When the MMU is off
(MMUCR.AT = 0), access is always performed according to the TC bit in PTEA. When the TC bit
is cleared to 0, bits A5W2 to A5W0 in WCR2 and bits A5PCW1 to A5PCW0, A5TED2 to
A5TED0, and A5TEH2 to A5TEH0 in PCR are selected. When TC is set to 1, bits A6W2 to
A6W0 in WCR2 and bits A6PCW1 to A6PCW0, A6TED2 to A6TED0, and A6TEH2 to A6TEH0
in PCR are selected.
Access to a PCMCIA interface area by the DMAC is always performed using the DMAC's
CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values.
Bits AnPCW1 and AnPCW0 in PCR can be used to set the number of wait cycles as 0, 15, 30, or
50 to be inserted in a low-speed bus cycle. This value is added to the number of inserted wait
cycles specified by WCR2. Bits AnTED2 to AnTED0 in PCR (with a setting range from 0 to 15)
can be used to retain the RD and WE1 signal addresses and the CS, CE2A, CE2B, and REG setup
times. Bits AnTEH2 to AnTEH0 in PCR (with a setting range from 0 to 15) can also be used to
retain the RD and WE1 signal addresses and the CS, CE2A, CE2B, and REG data hold times.
Bits A5IW2 to A5IW0 and A6IW2 to A6IW0 in WCR1 are used to set the number of wait cycles
between cycles. The selected number of wait cycles between cycles depends only on the area
accessed (area 5 or 6). When area 5 is accessed, bits A5IW2 to A5IW0 are selected, and when area
6 is accessed, bits A6IW2 to A6IW0 are selected.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the bus width that
was set. The first access is performed on the data where there was an access request, and the
remaining accesses are performed on the 32-byte boundary data in wraparound mode. The bus is
not released during this operation.
SA1
0
1
0
1
SA0
0
1
0
1
0
1
0
1
Description
Reserved (Setting prohibited)
Dynamic I/O bus sizing
8-bit I/O space
16-bit I/O space
8-bit shared memory
16-bit shared memory
8-bit attribute memory
16-bit attribute memory
Rev. 2.00 Feb. 12, 2010 Page 349 of 1330
REJ09B0554-0200