HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 489

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• DMARSRB
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Note: n = 4 to 7
Bit Name
CH4WEN
CH4RS6
CH4RS5
CH4RS4
CH4RS3
CH4RS2
CH4RS1
CH4RS0
CH5WEN
CH5RS6
CH5RS5
CH5RS4
CH5RS3
CH5RS2
CH5RS1
CH5RS0
CH6WEN
CH6RS6
CH6RS5
CH6RS4
CH6RS3
CH6RS2
CH6RS1
CH6RS0
CH7WEN
CH7RS6
CH7RS5
CH7RS4
CH7RS3
CH7RS2
CH7RS1
CH7RS0
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/(W)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)
R/W
R/W
R/W
R/W
R/(W)
R/(W)
R/W
R/(W)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)
R/W
R/W
R/W
R/W
R/(W)
R/(W)
R/W
Description
CHnRS6 to CHnRS0 specify transfer request sources to
each channel. DMARSRB bits are allocated to channels
0 to 3. When writing to the CHnRS6 to CHnRS0 bits for
each channel, simultaneously write 1 to the CHnWEN
bit. Clearing the CHnWEN bit to 0 will not change the
values in the CHnRS6 to CHnRS0 bits of each channel
and retain the previous values. The CHnWEN bit is
write-enabled, but it does not retain the written value and
is always read as 0.
CHnRS[6:0]
H'00: Unused or auto-request, TMU input capture
H'10: DREQ0*
H'11: DREQ1*
H'12: DREQ2*
H'13: DREQ3*
H'20: SCIF(0) Transmit-data-empty
H'21: SCIF(0) Receive-data-full
H'22: SCIF(1) Transmit-data-empty
H'23: SCIF(1) Receive-data-full
H'24: SCIF(2) Transmit-data-empty
H'25: SCIF(2) Receive-data-full
H'26: HSPI Transmit data
H'27: HSPI Receive data
H'28: SIM Transmit data empty
H'29: SIM Receive-data-full
H'2B: MMC FIFO ready
H'2C: ADC AD conversion end data transfer
H'2D: Setting prohibited
H'2E: Setting prohibited
H'7F: --*
Other than above: Setting prohibited
Notes: 1. This setting is valid only in DMABRG mode.
interrupt
2. Use this setting when the DMA transfer is
2
Rev. 2.00 Feb. 12, 2010 Page 405 of 1330
It is invalid in external request 2-channel
mode (channels 2 to 7 cannot accept
external requests).
complete with the request in DMAC retained
(DMARCR.REXn = 1). See (3) Notes on
Transfer End in section 11.4.6, Ending DMA
Transfer.
1
1
1
1
REJ09B0554-0200