HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 427

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
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D31–D0
(read)
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
CKIO
Bank
Figure 10.31 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8)
Figure 10.31 shows an example of the basic timing of a burst-read. To allow the connection of
a lower-speed DRAM, the bits in WCR2 and MCR can be set to increase the number of cycles.
Bits RCD1 and RCD0 in MCR can be used to specify the number of cycles from the ACTV
command output cycle Tr to the READA command output cycle Tc1, where setting values of
1, 2, or 3 correspond to 2, 3, or 4 cycles, respectively. When two or more cycles are specified,
the Trw cycle for issuing of NOP commands to the synchronous DRAM is inserted between
the Tr and Tc cycles. Bits A2W2 to A2W0 and A3W2 to A3W0 in WCR2 can be used to set
the number of cycles from the READA command output cycle Tc1 to cycle Td1 where the first
read data is received. The number of cycles from 1 to 5 is specifiable independently for areas 2
and 3. Note that this number of cycles is equal to the number of CAS latency cycles of the
synchronous DRAM.
Tr
Row
Row
Row
Trw
Tc1
Tc2
Tc3 Tc4/Td1
c1
Td2
c2
Td3
c3
Rev. 2.00 Feb. 12, 2010 Page 343 of 1330
Td4
c4
Td5
c5
Td6
c6
Td7
c7
REJ09B0554-0200
Td8
c8
Tpc

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