HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 376

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.5.11 Synchronous DRAM Mode Register (SDMR)
SDMR is a 16-bit write-only virtual register that is written to via the synchronous DRAM address
bus, and sets the mode of the area 2 and area 3 synchronous DRAM.
Settings for the SDMR register must be made before accessing synchronous DRAM.
Initial value:
Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register,
if the value to be set is "X" and the SDMR register address is "Y", value "X" is written to the
synchronous DRAM mode register by performing a write to address X + Y. When the
synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to
A2 of this LSI, and A1 of the synchronous DRAM is connected to A3 of this LSI, the value
actually written to the synchronous DRAM is the value of "X" shifted 2 bits to the right.
For example, to write H'0230 to SDMR in area 2, arbitrary data is written to address H'FF90 0000
(address "Y") + H'08C0 (value "X") (= H'FF90 08C0). As a result, H'0230 is written to the SDMR
register. The range of value "X" is H'0000 to H'0FFC.
Rev. 2.00 Feb. 12, 2010 Page 292 of 1330
REJ09B0554-0200
Bit
2
1
0
R/W:
Bit:
Bit
Name
A6TEH2
A6TEH1
A6TEH0
15
W
-
14
W
-
Initial
Value
0
0
0
13
W
-
12
W
-
R/W
R/W
R/W
R/W
11
W
-
10
W
-
Description
OE/WE Negation-Address Delay A6
These bits set the address hold delay time after OE/WE
negation in the connected PCMCIA interface. The
setting of these bits is selected when the PCMCIA
interface access TC bit is 1.
000:
001:
010:
011:
100:
101:
110:
111:
W
9
-
W
Wait cycles to be Inserted
0
1
2
3
6
9
12
15
8
-
W
7
-
W
6
-
W
5
-
W
4
-
3
W
-
2
W
-
1
W
-
0
W
-