HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 458

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Bus State Controller (BSC)
10.6.9
Waits between Access Cycles
A problem associated with higher operating frequencies for off-chip memory buses is that the data
buffer turn-off after completion of a read from a low-speed device may be too slow, causing a
collision with the data in the next access, and resulting in lower reliability or malfunctions. To
prevent this problem, this module provides a data collision prevention function. It stores the
preceding access area and the type of read/write and inserts a wait cycle before the access cycle if
there is a possibility of a bus collision when the next access is started. The process for wait cycle
insertion consists of inserting idle cycles between access cycles as shown in section 10.5.5, Wait
Control Register (WCR1). When this LSI performs consecutive write cycles, the data transfer
direction is fixed (from this LSI to other memory), and there is no problem. Also, for read accesses
to the same area, generally, data is output from the same data buffer, and no wait cycle is inserted.
If bits AnIW2 to AnIW0 (n = 0 to 6) in WCR1 are used to set idle cycles between accesses, the
number of inserted idle cycles is only the specified number of idle cycles minus the number of idle
cycles specified by the bits.
When bus arbitration is performed, the bus is released after wait cycles are inserted between
cycles.
In single address mode DMA transfer from an I/O device to memory, the I/O device speed
determines the data on the bus. When a low-speed I/O device is used, a wait time equivalent to the
output buffer turn-off time must be inserted between cycles. When a high-speed memory is used,
the memory may be unable to run at full speed since insertion of waits between cycles may be
required to adjust to the speed of a low-speed device for enabling DMA transfer.
Waits between cycles can be specified with bits DMAIW2 to DMAIW0 in wait control register 1
(WCR1) for single address mode DMA transfer from an I/O device to memory. The number of
waits that can be inserted should be in the range from 0 to 15. A number of waits specified by the
DMAIW2 to DMAIW0 bits are inserted in single address DMA transfers to all areas.
In dual address mode DMA transfer, the normal wait between cycles specified by bits AnIW2 to
AnIW0 (n = 0 to 6) is inserted.
Rev. 2.00 Feb. 12, 2010 Page 374 of 1330
REJ09B0554-0200