HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 186

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Rev. 2.00 Feb. 12, 2010 Page 102 of 1330
REJ09B0554-0200
(e) Flow dependency (cont)
(g) Anti-flow dependency
(f) Output dependency
LDS
FLOAT FPUL,FR0
LDS
FLOAT FPUL,R1
FTRC
STS
FTRC
STS
FSQRT FR4
FMOV
FADD
FMOV
FTRV
FMOV @R1,XD0
FADD DR0,DR2
FMOV FR4,FR1
XMTRX,FV0
R0,FPUL
R1,FPUL
FR0,FPUL
FPUL,R0
FR1,FPUL
FPUL,R1
FR0,FR4
DR0,DR2
FR0,FR3
Figure 5.3 Examples of Pipelined Execution (cont)
I
I
I
I
I
I
I
I
I
I
D
D
D
D
D
D
I
D
D
D
I
I
I
D
2 stall cycles
EX
F1
F1
F1
F1
10 stall cycles = latency (11) - 1
D
D
D
F0
D
d
d
d
I
I
6 stall cycles = longest latency (8) - 2
EX
NA
F1
EX
F1
F1
F1
F2
F2
F2
F2
F1
F0
D
d
d
d
D
5 stall cycles
Effectively 1-cycle latency for consecutive LDS/FLOAT instructions
F3
F2
NA
FS
NA
EX
F1
F2
FS
FS
F2
F1
F1
F2
F1
EX
F2
F0
FS
d
d
d
S
FS
FS
F2
NA
F2
F1
FS
F2
F1
NA
F2
F1
F0
FS
FS
S
S
d
d
Effectively 1-cycle latency for consecutive
FTRC/STS instructions
FS
FS
F2
F1
FS
F2
F2
FS
F1
F1
F1
S
S
FS
F2
EX
F1
F2
FS
F2
F1
FS
F2
MA
FS
FS
FS
F2
EX
F2
F1
FS
The registers are written-back
in program order.
11-cycle latency
FR3 write
7-cycle latency for lower FR
FS
NA
F2
S
FS
FR2 write
8-cycle latency for upper FR
FS
S

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