HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 251

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.4
7.4.1
When the IC is enabled (ICE = 1 in CCR) and instruction fetches are performed by means of an
effective address from a cacheable area, the instruction cache operates as follows:
1. The tag and V bit are read from the cache line indexed by effective address bits [12:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
3. Cache hit
4. Cache miss
7.4.2
Setting the IIX bit in CCR to 1 enables IC indexing to be performed using bit [25] of the effective
address. This is called IC index mode. In normal mode, with the IIX bit in CCR cleared to 0, IC
indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC
to be handled as two 4-Kbyte areas by means of effective address bit [25], providing efficient use
of the cache.
translation by the MMU:
The data indexed by effective address bits [4:2] is read as an instruction from the data field of
the cache line indexed by effective address bits [12:5].
Data is read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and when the corresponding data arrives in the
cache, the read data is returned to the CPU as an instruction. When reading of one line of data
is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is
written to the V bit.
• If the tag matches and the V bit is 1
• If the tag matches and the V bit is 0
• If the tag does not match and the V bit is 0
• If the tag does not match and the V bit is 1
Instruction Cache Operation
Read Operation
IC Index Mode
Rev. 2.00 Feb. 12, 2010 Page 167 of 1330
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REJ09B0554-0200