HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1159

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

30.3.5
LDSARU sets the start address from which data is fetched by the LCDC for display of the LCDC
panel. When a DSTN panel is used, this register specifies the fetch start address for the upper side
of the panel.
Initial value:
Initial value:
Notes: 1.
Bit
31 to 28 ⎯
27, 26
25 to 0
R/W:
R/W:
Bit:
Bit:
2.
LCDC Display Start Address Register - Upper (LDSARU)
SAU15 SAU14 SAU13 SAU12 SAU11 SAU10
Bit Name
⎯
SAU25
to
SAU0
R/W
31
15
R
0
0
-
The minimum alignment unit of LDSARU is 512 bytes when the hardware rotation
function is not used. Write 0 to the lower nine bits. When using the hardware rotation
function, set the LDSARU value so that the upper-left address of the image is aligned
with the 512-byte boundary.
When the hardware rotation function is used (ROT = 1), set the lower-left address of
the image which can be calculated from the display image size in this register. The
equation below shows how to calculate the LDSARU value when the image size is 240
× 340 and LDLAOR = 256. The LDSARU value is obtained not from the panel size but
from the memory size of the image to be displayed. Note that LDLAOR must be a
binary exponential at least as large as the horizontal width of the image. For the upper
left address, calculating backwards using the LDSARU value results in LDSARU − 256
(LDLAOR value) × (320 − 1), so make sure it is set within the 512-byte boundary.
LDSARU = (upper-left address of image) + 256 (LDLAOR value) × 319 (line)
R/W
30
14
-
R
0
0
R/W
29
13
Initial Value
All 0
All 1
All 0
R
0
0
-
R/W
28
12
R
0
0
-
R/W
27
11
R
1
0
-
R/W
R
R
R/W
R/W
26
10
R
1
0
-
SAU25 SAU24 SAU23 SAU22 SAU21 SAU20 SAU19 SAU18 SAU17 SAU16
SAU9 SAU8 SAU7 SAU6 SAU5
R/W
R/W
25
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
These bits are always read as 1. The write value
should always be 1.
Start Address for Upper Display Panel Data Fetch
The start address for data fetch of the display data
must be set within the synchronous DRAM area of
area 3.
0
9
0
R/W
R/W
24
0
8
0
R/W
R/W
23
0
0
7
Rev. 2.00 Feb. 12, 2010 Page 1075 of 1330
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
SAU4
R/W
R/W
20
0
4
0
SAU3 SAU2 SAU1 SAU0
R/W
R/W
19
0
3
0
REJ09B0554-0200
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0