HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1129

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Bit
13
12
Bit
Name
ADST
DMASL
Initial
Value
0
0
R/W
R/W
R/W
Description
A/D Start
Starts or stops A/D conversion. This bit remains set to 1
during A/D conversion. It can also be set to 1 by external
trigger input (ADTRG) pin (except in multi mode).
0: A/D conversion is stopped
1:
DMAC Select
Selects an interrupt or activation of the DMAC due to the
end of A/D conversion. Do not change the DMASL bit
setting during A/D conversion.
0: An interrupt by the end of A/D conversion is selected
1: Activation of the DMAC by the end of A/D conversion is
selected
Single mode: A/D conversion starts. This bit is cleared
to 0 automatically when conversion on the specified
channel ends. Even when the ADST bit is cleared to 0
(by software), A/D conversion does not stop (0 cannot
be written to this bit during A/D conversion).
Multi mode: A/D conversion starts. This bit is cleared
to 0 automatically when conversion on the specified
channels has been performed for one cycle. When
the ADST bit is cleared to 0 (by software), A/D
conversion stops when the currently executed
channel ends.
Scan mode: A/D conversion starts. A/D conversion
continues without a break until the ADST bit is cleared
to 0 by software or until all registers are initialized by
a power-on or manual reset or in hardware standby,
module standby, or software standby mode. For the
standby modes, refer to section 29.7.4, Notes on
Standby Modes.
Rev. 2.00 Feb. 12, 2010 Page 1045 of 1330
REJ09B0554-0200

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