HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 783

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(2) Load the master control register, first data byte and address:
(a) Set address of slave being accessed to the master address register and the STM1 bit (write
(b) Set the first byte to be transmitted to the transmit data register.
(c) Set the master control register to 89h.
(3) Wait for the address to be output:
(a) Wait for master events (interrupts by the MAT and MDE bits in the master status register).
(b) Set the master control register to 88h (the master device holds the SCL low level until the
(c) Reset the MAT and MDE bits to 0.
(4) Monitor the progress of data byte transmission:
(a) Wait for a master event (the MDE bit in the master status register).
(b) Load the next data byte into the transmit data register.*
Note: * There is no need to observe the limitation that "execution must continue until the first
(c) Reset the MDE bit.
(5) Wait for the end of transmission:
(a) Wait for a master event (the MST bit in the master status register).
(b) Reset the MST bit after checking MNR (master NACK received).
mode: 0).
(MDBS = 1, MIE = 1, and ESG = 1)
MDE bit is cleared in order to suspend the data transmission).
If only one data byte is to be transmitted, set the master control register 8Ah. (This enables the
stop generation). This generates a stop on the bus as soon as one byte has been transmitted.
Clear the MDE bit after setting the last transmit byte. After transmission of the last byte is
started, MDE is generated. Before clearing the MDE bit, set 8Ah in the master control register
(this must be done before the last transmission byte is completely output).
(Set the force stop bit.)
data byte has been output" in this case.
Rev. 2.00 Feb. 12, 2010 Page 699 of 1330
Section 19 I
REJ09B0554-0200
2
C Bus Interface