HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 79

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 10.16 Example of Correspondence between SH7760 and Synchronous DRAM Address
Table 10.17 Availability of Pipelined Access for Cycles...........................................................336
Table 10.18 Relationship between Address and CE When Using PCMCIA Interface ..............350
Section 11 Direct Memory Access Controller (DMAC)
Table 11.1
Table 11.2
Table 11.2
Table 11.3
Table 11.4
Table 11.5 (1) Data Alignment for Receive Slot Data and External Bus.....................................419
Table 11.5 (2) Data Alignment for Transmit Slot Data and External Bus ...................................419
Table 11.6
Table 11.7
Table 11.8
Table 11.9 (1) External Request Transfer Sources and Destinations in External Request
Table 11.9 (2) External Request Transfer Sources and Destinations in DMABRG Mode ..........439
Table 11.10 DMAC Interrupt-Request Codes ............................................................................464
Table 11.11 (1) Conditions for Transfer between External Memory and External Device with
Table 11.11 (2) Conditions for Transfer between External Memory and External Device with
Table 11.12 Data Alignment between Peripheral Bus and USB Bridge Bus .............................482
Table 11.13 Data Alignment between External Bus and USB Bridge Bus ................................483
Section 12 Clock Pulse Generator (CPG)
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.4
Section 13 Watchdog Timer (WDT)
Table 13.1
Table 13.1
Section 14 Power-Down Modes
Table 14.1
Table 14.2
Table 14.3
Pins (32-Bit Bus Width, AMX2 to AMX0 = 000, AMXEXT = 0) ........................321
Pin Configuration ...................................................................................................382
Register Configuration (1)......................................................................................383
Register Configuration (2)......................................................................................386
External Request 2-Channel Mode (DMS[1:0] in DMAOR = 00).........................398
DMABRG Mode (DMS[1:0] in DMAOR = 11) ....................................................399
Selecting External Request Mode with RS Bits .....................................................426
Supported DMA Transfers .....................................................................................432
Relationship between DMA Transfer Type, Request Mode, and Bus Mode .........437
DACK, and Corresponding Register Settings ........................................................465
DACK, and Corresponding Register Settings ........................................................466
Pin Configuration and Function of an Oscillation Circuit......................................490
Clock Operating Modes..........................................................................................491
FRQCR Settings and CPU Clock Frequencies.......................................................492
Register Configuration (1)......................................................................................493
Register Configuration (2)......................................................................................493
Register Configuration (1)......................................................................................504
Register Configuration (2)......................................................................................504
Status in Power-Down Modes ................................................................................512
Pin Configuration ...................................................................................................513
Register Configuration (1)......................................................................................513
2-Channel Mode...................................................................................................438
Rev. 2.00 Feb. 12, 2010 Page lxxvii of lxxxii
REJ09B0554-0200