HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 817

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 Serial Sound Interface (SSI) Module
(2) Slave Transmitter
This mode cannot be used.
(3) Master Receiver
This mode allows the SSI module to receive a serial bit stream from another device and store it in
memory.
The shift register clock can be supplied from an external device or from an internal clock.
The word select pin is used as an output flow control. The module always asserts the word select
signal to indicate it can receive more data continuously. It is the responsibility of the host CPU to
ensure it can transmit data to the SSI module in time to ensure no data is lost.
(4) Master Transmitter
This mode allows the module to transmit a serial bit stream from internal memory to another
device.
The shift register clock can be supplied from an external device or from an internal clock.
The word select pin is used as an output flow control. The module always asserts the word select
signal to indicate it will transmit more data continuously. Word select signal is not asserted until
the first word is ready to transmit however. It is the responsibility of the receiving device to ensure
it can receive the serial data in time to ensure no data is lost.
When the configuration for data transfer is completed, the SSI module can work with the
minimum interaction with CPU. The CPU specifies settings for the SSI module and DMAC then
handles overflow/ underflow interrupts if required.
20.4.4
Operation Modes
There are three modes of operation: configuration, enabled and disabled. Figure 20.20 shows the
transition diagram between these operation modes.
Rev. 2.00 Feb. 12, 2010 Page 733 of 1330
REJ09B0554-0200