HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1103

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 28 User Debug Interface (H-UDI)
Section 28 User Debug Interface (H-UDI)
The H-UDI is serial input/output interface using the pin functions and transfer protocol compliant
with JTAG (IEEE 1149.4: IEEE Standards Test Access Port and Boundary-Scan Architecture)
standards.
The H-UDI is also used for emulator connection. Do not use H-UDI functions when using an
emulator. Refer to the appropriate emulator manual for the method of connecting the emulator.
The H-UDI consists of six pins: TCK, TMS, TDI, TDO, TRST, and ASEBRK/BRKACK. The pin
functions and serial communication protocol comprise a subset of the JTAG standard. This LSI
has additional six pins for emulator connection: (AUDSYNC, AUDCK, and AUDATA[3] to
AUDATA[0]). The pins for emulator connection can also be multiplexed for other functions and
are assigned to the module specified by the settings of IPSELR in the PFC.
The H-UDI contains two separate TAP controllers, one for controlling the boundary-scan function
and another for other functions. Asserting TRST, for example at a power-on reset, activates the
boundary-scan TAP controller. To use the TAP controller for other functions, input a switchover
command to the H-UDI. The CPU has no access to the boundary-scan TAP controller.
Figure 28.1 shows a block diagram of the H-UDI. To initialize the TAP (Test Access Port)
controller, control registers and boundary-scan TAP controller, assert TRST active low, or set the
TMS pin to 1 and apply TCK for 5 or more cycles. This initialization sequence is independent of
the reset pin for this LSI. Other circuits are initialized by the reset pin.
The H-UDI has four registers: SDIR, SDDR (SDDRH and SDDRL), and SDINT. SDBSR
configures the JTAG-compliant boundary-scan system, SDIR is used for commands, SDDR is
used for data, and SDINT is used for H-UDI interrupts. SDIR is directly accessed from the TDI
and TDO pins.
Rev. 2.00 Feb. 12, 2010 Page 1019 of 1330
REJ09B0554-0200