HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 723

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Bit
3
Bit
Name
PER
Initial
Value
0
R/W
R/W
Description
Parity Error
Indicates that a parity error has occurred during reception,
resulting in abnormal termination.
0: Indicates that reception is in progress, or that reception
[Clearing Conditions]
1: Indicates that a parity error occurred during reception.*
[Setting Condition]
Notes: 1. Clearing the RE bit in SISCR to 0 will retain the
was completed normally.*
On reset
When 0 is written to PER
When the number of logic 1 digits combined in the
receive data and parity bit does not match the setting of
the even/odd parity specified by the serial mode register’s
(SISMR) O/E bit during reception.
2. In the T = 0 mode, the receiver does not transfer
previous state without affecting the PER flag.
the data received when a parity error occurs to
SIRDR, and sets the RDRF flag.
On the other hand, in the T = 1 mode, the data
received when a parity error occurs is sent to
SIRDR, and the RDRF flag is set.
When a parity error occurs, clear the PER flag to
0 before the sampling timing for the next parity
bit. When PER is set to 1, data reception can
continue. However, the PER flag will not be
cleared when reception is completed
successfully.
Rev. 2.00 Feb. 12, 2010 Page 639 of 1330
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REJ09B0554-0200
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