HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1024

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

DMA control register
Interrupt control register 2
Interrupt status register 2
Receive data timing select register
Register Name
Note: * After exiting hardware standby mode, this LSI enters the power-on reset state caused
26.3.1
MODER is an 8-bit readable/writable register that specifies the MMCIF operating mode. The
following sequence should be repeated when the MMCIF uses the multimedia card: Send a
command, wait for the end of the command sequence and the end of the data busy state, and send
a next command.
The series of operations from command sending, command response reception, data
transmission/reception, and data response reception is called as the command sequence. The
command sequence starts from sending a command by setting the START bit in CMDSTRT to 1,
and ends when all necessary data transmission/reception and response reception have been
completed. The multimedia card supports the data busy state such that only the specific command
is accepted to write/erase data to/from the flash memory in the card during command sequence
execution and after command sequence execution has ended. The data busy state is indicated by a
low level output from the card side to the MCDAT pin.
Rev. 2.00 Feb. 12, 2010 Page 940 of 1330
REJ09B0554-0200
Bit
7 to 1
0
Mode Register (MODER)
Bit
Name
—
MODE
by the RESET pin.
Initial
Value
All 0
0
Initial value:
R/W:
Bit:
R/W
R
R/W
-
R
7
0
DMACR
INTCR2
INTSTR2
RDTIMSEL H'00
Abbrev.
6
0
R
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operating Mode
Specifies the MMCIF operating mode.
0: Operates in MMC mode
1: Setting prohibited
H'00
H'00
H'0x
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
R
5
0
-
4
0
R
-
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
H'00
H'00
H'0x
H'00
R
3
-
0
2
-
0
R
R
0
1
-
Retained
Retained
Retained
Retained
Sleep
by Sleep
Instruction/
Deep Sleep
MODE
R/W
0
0
by
Hardware
*
Standby
by
Software/
Each
Module
Retained
Retained
Retained
Retained