HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 763

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

19.3.9
Initial value:
Initial value:
Bit
31 to 8
7 to 2
1, 0
R/W:
R/W:
Bit:
Bit:
Clock Control Register (ICCCR)
Bit Name
⎯
SCGD
CDF
31
15
R
R
0
0
-
-
30
14
R
R
-
-
0
0
29
13
R
R
0
0
-
-
Initial Value
All 0
All 0
All 0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R
R/W
R/W
R/W
26
10
R
R
-
0
-
0
25
R
R
-
0
9
-
0
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
SCL Clock Generation Divider
In master mode operation, the SCL clock is
generated from the internal clock frequency using
the SCGD value as the division ratio. In slave
mode operation, if SCL is held low to stall the bus
by data overflow, this clock is also generated from
the internal clock. Accordingly, SCGD must be
programmed for master and slave operating
modes. The formula expressing the relationship is:
Equation 2 SCL rate calculation
Recommended settings for CDF and SCGD for
various CPU rates and the two I
given in table 19.3.
Clock Division Factor
The internal clocks for most of the blocks in the I
bus interface module are divided from peripheral
bus clock. The internal I
the peripheral clock using the value of CDF as the
division ratio:
Equation 1 I
The minimum setup and hold times on the SMA
line relative to the SCL line on the bus should be
met.
The clock frequency is to ensure that the glitch
filtering will operate with glitches of up to 50 ns (as
described in the fast mode I
Note: CDF must be set to a value that the clock
frequency (IICck) is less than 20 MHz.
24
R
R
0
8
0
-
-
SCL freq = IICck / (20 + SCGD * 8)
R/W
23
R
0
7
0
-
IICck = Pck / (1 + CDF)
Rev. 2.00 Feb. 12, 2010 Page 679 of 1330
R/W
2
22
C internal clock frequency calculation
R
0
0
6
-
R/W
21
R
0
5
0
-
SCGD
R/W
2
20
C clock is generated from
Section 19 I
R
0
4
0
-
2
C specifications).
R/W
19
R
0
3
0
-
2
C bus speeds are
REJ09B0554-0200
R/W
18
R
0
2
0
-
2
C Bus Interface
R/W
17
R
0
1
0
-
CDF
R/W
16
R
0
0
0
-
2
C