HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 840

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits
3
2
1
0
21.3.5
Each enable bit in HcInterruptEnable corresponds to the related hardware interrupt bit in
HcInterruptStatus. A hardware interrupt is generated when bits in HcInterruptStatus are set to1,
the corresponding bits in HcInterruptEnable are set to 1, and HcInterruptEnable.MIE = 1.
Writing 1 to a bit in this register sets the corresponding bit to 1, while writing 0 does not clear the
bit to 0 but leaves it unchanged. Reading this register will return the current value of this register.
Rev. 2.00 Feb. 12, 2010 Page 756 of 1330
REJ09B0554-0200
Interrupt Enable Register (HcInterruptEnable)
Bit Name
RD
SF
WDH
SO
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Resume Detected
HC sets this bit to 1 when detecting the transmission
of a resume signal by a USB device. This bit is not
set when HCD sets USB resume state.
0: A USB device is not asserting a resume signal
1: A USB device is asserting a resume signal
Start of Frame
HC sets this bit to 1 when each frame is started and
after the HccaFrameNumber is updated. HC
simultaneously generates the SOF token.
0: Frame is not started or HccaFrameNumber is not
1: Frame is started and HccaFrameNumber is
Writeback Done Head
HC sets this bit to 1 immediately after writing
HcDoneHead to HccaDoneHead. HccaDoneHead is
not updated until this bit is cleared. HCD should clear
this bit only after the content of HccaDoneHead has
been stored.
0: HccaDoneHead is retained
1: The value in HcDoneHead is written to
HccaDonehead
HC sets this bit to 1 when the USB schedule has
overrun in the current frame after
HccaFrameNumber is updated. Scheduling overrun
also increments the SOC bit in HcCommandStatus.
0: The USB schedule has not overrun in the current
1: The USB schedule has overrun in the current
Scheduling Overrun
updated
updated
frame
frame