HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 848

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

21.3.14 Frame Interval Register (HcFmInterval)
HcFmInterval consists of a 14-bit FI value that indicates the frame bit time interval (interval
between two consecutive SOFs) and a 15-bit FSMPS value that indicates the maximum packet
size that is transmitted and received at full speed by HC without causing scheduling overrun. HCD
minutely adjusts the frame interval by updating the value in each SOF.
Initial value:
Initial value:
Bit
31
30 to
16
15, 14
13 to 0
Rev. 2.00 Feb. 12, 2010 Page 764 of 1330
REJ09B0554-0200
R/W:
R/W:
Bit:
Bit:
Bit Name
FIT
FSMPS
⎯
FI
R/W
FIT
31
15
R
0
0
-
R/W
30
14
-
R
0
0
R/W
R/W
Initial Value
0
All 0
All 0
H'2EDF
29
13
0
1
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
1
R/W
R/W
R/W
R
R/W
R/W
R/W
26
10
0
1
R/W
R/W
25
0
9
1
Description
Frame Interval Toggle
This bit is toggled by HCD whenever it loads a new
value into FI.
Largest Data Packet
This bit specifies a value to be loaded into the
Largest Data Packet Counter at the beginning of
each frame. The counter value represents the
maximum amount of data in bits
transmittable/receivable by HC in a single
transaction at any given time without causing
scheduling overrun. The bit value is calculated by
HCD.
Reserved
These bits are always read as 0. Always write 0 to
this bit.
Frame Interval
This bit specifies the interval between two
consecutive SOFs in bit times. The nominal value is
set to be 11999.
HCD should store the current value of this bit before
resetting HC. Setting the HCR bit in
HcCommandStatus will have the HC reset this bit to
its nominal value. HCD may choose to restore the
stored value upon the completion of the reset
sequence.
R/W
R/W
24
0
8
0
FSMPS
R/W
R/W
23
0
7
1
FI
R/W
R/W
22
1
0
6
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
1
R/W
R/W
19
0
3
1
R/W
R/W
18
0
2
1
R/W
R/W
17
0
1
1
R/W
R/W
16
0
0
1