HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 650

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

16.4.9
Each of the two updown-counters can operate in rotary mode. This treats the two input signals as
encoded, as shown in figure 16.11. A rotary switch generates the following waveforms depending
on the direction. The direction is determined by the value of A when a falling edge is detected on
the B input; if A is 1, the direction is left (down is 1) and if A is 0, the direction is right (up is 1).
A is pin 0 and pin 2. B is pin 1 and pin 3. The interrupt edge bit in channels 3 to 0 will be set
whenever a change in the counter value occurs. If a counter overflow or underflow occurs, the
interrupt overflow bit in channels 3 to 0 will be set as well.
16.4.10 Timer Frequency
The frequency of the free running timer and the 16-bit timers can be altered under software control
to be 1 of 4 frequencies. Each 16-bit timer can have an independent clock.
16.4.11 Standby Mode
CMT allows clock gating to reduce power consumption. The module standby mode can be
executed by controlling bit 17 in the Clock Stop Register 00 (CLKSTP00).
To wake up the module, bit 17 in the Clock Stop Clear Register 00 (CLKSTPCLR00) must be
enabled. After enabling this bit all access to CMT can be possible.
To power down the module, the following procedure is required.
1.
2.
3.
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All channels needs to be in input capture mode (CMTCTL.OP3 - OP0=0000).
The active edge for each channel needs to be disabled (CMTCFG.ED3 - ED0=00).
Disable bit 17 in the Clock Stop Register 00 (CLKSTP00).
Rotary Mode
Right rotation
Figure 16.11 Rotary Mode
A (data)
B (edge)
Left rotation