HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 43

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.4
9.5
9.6
Section 10 Bus State Controller (BSC).............................................................247
10.1 Features ............................................................................................................................ 247
10.2 Input/Output Pins ............................................................................................................. 250
10.3 Overview of Areas ........................................................................................................... 251
10.4 PCMCIA Support............................................................................................................. 255
10.5 Register Descriptions ....................................................................................................... 258
10.6 Operation.......................................................................................................................... 298
9.3.6
Interrupt Sources .............................................................................................................. 235
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
Operation.......................................................................................................................... 243
9.5.1
9.5.2
9.5.3
Interrupt Response Time .................................................................................................. 246
10.5.1 Bus Control Register 1 (BCR1) .......................................................................... 260
10.5.2 Bus Control Register 2 (BCR2) .......................................................................... 267
10.5.3 Bus Control Register 3 (BCR3) .......................................................................... 268
10.5.4 Bus Control Register 4 (BCR4) .......................................................................... 269
10.5.5 Wait Control Register 1 (WCR1)........................................................................ 271
10.5.6 Wait Control Register 2 (WCR2)........................................................................ 274
10.5.7 Wait Control Register 3 (WCR3)........................................................................ 281
10.5.8 Wait Control Register 4 (WCR4)........................................................................ 282
10.5.9 Memory Control Register (MCR) ....................................................................... 284
10.5.10 PCMCIA Control Register (PCR)....................................................................... 289
10.5.11 Synchronous DRAM Mode Register (SDMR) ................................................... 292
10.5.12 Refresh Timer Control/Status Register (RTCSR) ............................................... 294
10.5.13 Refresh Timer Counter (RTCNT)....................................................................... 296
10.5.14 Refresh Time Constant Register (RTCOR) ........................................................ 296
10.5.15 Refresh Count Register (RFCR) ......................................................................... 296
10.5.16 Accessing Refresh Control Related Registers..................................................... 297
10.6.1 Endian/Access Size and Data Alignment............................................................ 298
10.6.2 Areas ................................................................................................................... 305
10.6.3 SRAM Interface .................................................................................................. 310
10.6.4 Synchronous DRAM Interface............................................................................ 318
10.6.5 Burst ROM Interface........................................................................................... 345
10.6.6 PCMCIA Interface .............................................................................................. 348
Interrupt Mask Clear Registers 00, 04 (INTMSKCLR00, INTMSKCLR04) ..... 234
NMI Interrupt...................................................................................................... 235
IRQ Interrupts ..................................................................................................... 235
IRL Interrupts...................................................................................................... 235
Peripheral Module Interrupts .............................................................................. 237
Interrupt Exception Handling and Priority.......................................................... 238
Interrupt Operation Sequence ............................................................................. 243
Multiple Interrupts .............................................................................................. 245
Interrupt Masking with MAI Bit ......................................................................... 245
Rev. 2.00 Feb. 12, 2010 Page xli of lxxxii
REJ09B0554-0200