HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 838

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits
0
21.3.4
HcInterruptStatus indicates the status of various events that cause hardware interrupts. To generate
an interrupt, HC sets the corresponding bit in this register to 1 when HcInterruptEnable enables a
hardware interrupt with HcInterruptEnable.MIE = 1. HCD can clear a bit to 0 by writing 1 to
release the interrupt status. However, HCD cannot set any of these bits to 1.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 754 of 1330
REJ09B0554-0200
R/W:
R/W:
Bit:
Bit:
Interrupt Status Register (HcInterruptStatus)
Bit Name
HCR
31
15
R
R
0
0
-
-
R/W
OC
30
14
-
R
0
0
29
13
R
R
0
0
-
-
Initial Value
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R/W
R/W
26
10
R
R
-
0
-
0
25
R
R
-
0
9
-
0
Description
Host Controller Reset
HCD sets this bit to 1 to start software reset of HC.
The HC changes to the USB suspend state in which
most operational registers are reset, regardless of
which functional state the HC is in. However, access
to the InterrupRouting field in HcControl or access
without host bus is allowed. HC clears this bit to 0
upon completion of the reset operation. The reset
operation must be completed within 10μs. Setting
this bit to 1 does not either reset the root hub or
issue the subsequent reset signal to the downstream
port.
0: Software reset of HC is cancelled
1: Software reset of HC is started
24
R
R
0
8
0
-
-
23
R
R
0
7
0
-
-
RHSC FNO
R/W
22
R
0
0
6
-
R/W
21
R
0
5
0
-
R/W
UE
20
R
0
4
0
-
R/W
RD
19
R
0
3
0
-
R/W
SF
18
R
0
2
0
-
WDH
R/W
17
R
0
1
0
-
SO
R/W
16
R
0
0
0
-