HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 717

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
7
6
5
Bit
Name
TIE
RIE
TE
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
Enables or disables transmit data empty interrupt (SIMTXI)
requests when serial transmit data is transferred from SITDR
to SITSR, and the TDRE flag in SISSR is set to 1.
0: Disables transmit data empty interrupt (SIMTXI)
1: Enables transmit data empty interrupt (SIMTXI)
Note: * SIMTXI can be canceled by clearing either the TDRE
Receive interrupt enable
Enables or disables receive data full interrupt (SIMRXI)
requests, and transmit/receive error interrupt (SIMERI)
requests due to parity errors, overrun errors, and error signal
status, when serial receive data is transferred from SIRSR to
SIRDR, and the RDRF flag in SISSR register is set to 1.
0: Disables receive data full interrupt (SIMRXI) requests
1: Enables receive data full interrupt (SIMRXI) requests
Notes: 1. SIMRXI and SIMERI interrupt requests can be
Transmit Enable
Enables/disables serial transmission operations.
0: Disables transmission*
1: Enables transmission*
Notes: 1. The TDRE flag in SISSR register is fixed at 1.
requests*
requests
and transmit/receive error interrupt (SIMERI) requests*
and transmit/receive error interrupt (SIMERI) requests*
flag or TIE to 0.
2. In this state, if transmit data is written to SITDR,
2. Wait error interrupt (SIMERI) requests are enabled
canceled by clearing the RDRF flag or the PER,
ORER or ERS flag or the RIE bit to 0.
and disabled using the WAIT_IE bit in SISCR.
the transmission operation is started. Before
setting the TE bit to 1, SISMR and SISCMR must
always be set to determine the transmission
format.
Rev. 2.00 Feb. 12, 2010 Page 633 of 1330
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