HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1227

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

31.7
In this LSI, this function stops the clock supplied to the user break controller and is used to
minimize power consumption when the chip is operating. Note that, if you use this function, you
cannot use the user break controller.
31.7.1
Setting bit MSTP5 of the STBCR2 (inside the CPG) to 1 stops the clock supply and causes the
user break controller to enter the stopped state. Follow steps 1 to 5 below to set bit MSTP5 to 1
and enter the stopped state.
1. Initialize BBRA and BBRB to 0;
2. Initialize BRCR to 0;
3. Make a dummy read of BRCR;
4. Read STBCR2, then set bit MSTP5 in the read data to 1 and write the modified data back.
5. Make two dummy reads of STBCR2.
Make sure that, if an exception or interrupt occurs while performing steps 1 to 5, you do not
change the values of these registers in the exception handling routine.
Do not read from or write to BARA, BAMRA, BBRA, BARB, BAMRB, BBRB, BDRB,
BDMRB, and BRCR registers while the UBC clock is stopped. If the registers are read from or
written to, the value cannot be guaranteed.
31.7.2
The clock supply can be restarted by setting bit MSTP5 of STBCR2 (inside the CPG) to 0. The
user break controller can then be operated again. Follow steps 1 and 2 below to clear bit MSTP5 to
0 to cancel the stopped state.
1. Read STBCR2, then clear bit MSTP5 in the read data to 0 and write the modified data back;
2. Make two dummy reads of STBGR2.
As with the transition to the stopped state, if an exception or interrupt occurs while processing
steps 1 and 2, make sure that the values in these registers are not changed in the exception
handling routine.
User Break Controller Stop Function
Transition to User Break Controller Stopped State
Cancelling the User Break Controller Stopped State
Rev. 2.00 Feb. 12, 2010 Page 1143 of 1330
REJ09B0554-0200