HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 767

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Notes: 1. Values in parentheses ( ) indicate the number of empty stages in the transmit FIFO data
Bit
7
6
5
4
3
2
1
0
2. At power-on reset and manual reset, the reset operation is performed.
Bit Name
RTRG3
RTRG2
RTRG1
RTRG0
TTRG1
TTRG0
RFRST
TFRST
register (ICTXD) in each case.
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Receive FIFO Data Count Trigger
These bits specify the receive byte count to set
ICFSR.RDF. The RDF flag is set to 1 when the
receive byte count in ICRXD reaches the trigger
byte count set in these bits. The following settings
are available:
0000: 1
0001: 2
0010: 3
0011: 4
0100: 5
0101: 6
Transmit FIFO Data Count Trigger
These bits specify the receive byte count to set
ICFSR. TDFE. The RDF flag is set to 1 when the
receive byte count in ICTXD is equal to or smaller
than the trigger byte count set in these bits. The
following settings are available:
00: 8 (8)*
01: 4 (12)
10: 2 (14)
11: 0 (16)
Receive FIFO Data Register Reset
Disables the receive data in ICRXD and resets
ICRXD to the empty state.
0: The reset operation*
1: The reset operation is enabled
Transmit FIFO Data Register Reset
Disables the receive data in ICTXD and resets
ICTXD to the empty state.
0: The reset operation*
1: The reset operation is enabled
1
0110: 7
0111: 8
1000: 9
1001: 10
1010: 11
1011: 12
Rev. 2.00 Feb. 12, 2010 Page 683 of 1330
1100: 13
1101: 14
1110: 15
1111: 16
2
2
is disabled
is disabled
Section 19 I
REJ09B0554-0200
2
C Bus Interface