HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 154

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 70 of 1330
REJ09B0554-0200
Addressing
Mode
Register
indirect with
displacement
Indexed
register
indirect
GBR indirect
with
displacement
Indexed
GBR indirect
Instruction
Format
@(disp:4, Rn)
@(R0, Rn)
@(disp:8, GBR) Effective address is register GBR contents with
@(R0, GBR)
Effective Address Calculation Method
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
Effective address is sum of register Rn and R0
contents.
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
Effective address is sum of register GBR and R0
contents.
(zero-extended)
(zero-extended)
GBR
1/2/4
1/2/4
GBR
disp
disp
Rn
R0
R0
Rn
×
×
+
+
+
+
Rn + disp × 1/2/4
+ disp × 1/2/4
GBR + R0
Rn + R0
GBR
Calculation
Formula
Byte: Rn +
disp → EA
Word: Rn +
disp × 2 → EA
Longword:
Rn + disp × 4
→ EA
Rn + R0 →
EA
Byte: GBR +
disp → EA
Word: GBR +
disp × 2 → EA
Longword:
GBR + disp ×
4 → EA
GBR + R0 →
EA